The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor chip, a memory module and a method for testing the semiconductor chip.
In order to ensure the correct functioning of semiconductor chips, semiconductor chips are usually tested prior to delivery. In principle, there are two different procedures for this.
By way of example, it is possible to connect an external test device to the semiconductor chips and to check the semiconductor chips with the aid of this test device. A disadvantage here is that the semiconductor chips each have to be individually contact-connected, which is complicated given the large number of semiconductor chips on a wafer.
Furthermore, it is possible to integrate the test circuit into the semiconductor chip and to drive it externally via an interface. This method is known under the designation BIST (xe2x80x9cBuild In Self Testxe2x80x9d) in the semiconductor industry. In some cases, the test circuit also provides for a self-repair of the semiconductor chips. This method is also known as BISR (xe2x80x9cBuild In Self Repairxe2x80x9d). One disadvantage of the integrated test circuits is that they take up a considerable proportion of the area of the semiconductor chip. This leads to an unacceptable increase in the costs for fabricating the semiconductor chips.
It is accordingly an object of the invention to provide a semiconductor chip, a memory module and a method for testing the semiconductor chip, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a semiconductor chip and, in particular, a memory module which can be tested in a simple manner. It is a further object to provide for a simple test method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor chip, comprising:
a chip body having a first side and an opposite second side;
a multiplicity of external contacts including at least one contact on the first side of the chip body, at least one contact on the second side of the chip body, and a connection connecting the contacts and extending through the chip body.
By virtue of the looping-through of contacts of the semiconductor chip, these can be stacked on a control chip and be tested jointly with the aid of the control chip. This method is particularly advantageous if a large number of identical semiconductor chips are to be tested. This is the case with memory chips, in particular. It is also conceivable, in principle, to stack a large number of memory chips on top of one another in order thereby to increase the storage volume per memory module.
In the semiconductor chips, the data and address lines are looped through from one side of the semiconductor chip to the other side of the semiconductor chip.
The looping-through of the data and address lines affords the advantage that the semiconductor chips can be individually addressed via the data and address lines as in the case of a conventional memory module.
In accordance with an added feature of the invention, the semiconductor chip is a memory chip and the external contacts are contacts for data lines and address lines looped through from one side of the memory chip to an opposite side of the memory chip.
In accordance with an additional feature of the invention, the contact is a looped-through contact for serial data communication.
With the above and other objects in view there is also provided, in accordance with the invention, a memory module, comprising a control chip and a multiplicity of memory chips forming memory units stacked on the control chip, and at least one contact looped through from one side of a respective the memory chip to an opposite side of the memory chip.
In accordance with another feature of the invention, the memory chips have a multiplicity of looped-through contacts connected to the internal data lines, address lines, or command lines of the memory chip.
In accordance with a further feature of the invention, the looped-through contact is a line for serial data communication.
In accordance with again an added feature of the invention, the control chip is formed with a given minimum feature size that is larger than a minimum feature size of the memory chip stacked on the control chip.
In accordance with again an additional feature of the invention, the memory chips are contained in a wafer composite stacked onto a wafer with the control chips.
In accordance with again another feature of the invention, the control chip is configured to control a performance of a functional test of the memory chip.
With the above and other objects in view there is also provided, in accordance with the invention, a method of testing semiconductor chips, which comprises stacking the semiconductor chips on a control chip configured for testing a function of the semiconductor chips and forming contact between the control chip and the semiconductor chips with a contact looped through from one side of the semiconductor chips to another side of the semiconductor chips; and testing the function of the semiconductor chips.
In accordance with again another feature of the invention, a wafer composite of a multiplicity of semiconductor chips arranged next to one another is stacked on top of a wafer composite of control chips arranged next to one another.
In accordance with again a further feature of the invention, test signals supplied by the semiconductor chips are transmitted to the control chip via looped-through data, address or command lines. Also, the test signals may be transmitted via a serial line.
In accordance with a concomitant feature of the invention, control signals for initiating and performing a functional test of the semiconductor chip are generated with the control chip and the control signals are transferred to one of the semiconductor chips via the looped-through contact.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor chip, memory module and method for testing the semiconductor chip, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.